GABY WRITES to tell me I should start shipping containers from Xiamen Port.
And she says that Xiamen Greating Container Services Co is approved as a class A forwarder by the Ministry of Trade in the PRC.
Thanks Gaby. If we ever need containers of Tsing Tao sent this way, you will be the first to hear from us. If you want to ask Gaby about containers, drop her a line at www.sinotrans.com. She is waiting to take your call on +86-592-5678097. ♣
Gabbie Hales, that Friend of Friends just released this Trunk:
Here GOOD thing is Higher Internal MAIN Bandwidth. However, BAD thing is LESS Lanes, Although Each Lane should Have More data(Due to Higher Frequency), Good for Ultimate & Deep L1 Cacheing.
Think of 1 signal say 48 units per anything within, Each lane is 1 unit of time that signal carries one lane of info to comparrison unit, if computer is seeking data on that particular lane, it will activate gates starting up from L1 Cache. In other words if Signal where 480 units of X or O per anything, Each Lane would get 10 X or O, then gate flip to next lane, where its 10 units would hit comparrison unit. More Routing or discard, yet say lane one is display, two printer, three, front door bell, four all mysteries of universe. I think you see each is identifier & if needed, comparrison unit is sent needed (stored) signal string, EG: get ATI Catylist control center, so gates open, HDD dumpds files to DDRx memory & comparrison looks for what was requested. By then lanes are churning lots o’ ati catylyst control center files as seperate lanes, probably all 32, waiting for which to react to & its Found instructions sets more gates. Until computer is so fine tuned, it squeeks. Then Ultiee’ Licks Ice Cream Cone.
32 Lanes & 32 bits in Todays frequency just isn’t enough for Ultimate, I have been SCREAMING this for Over Two Years, its in ORIGINAL White Papers from Microsoft on Vista, Way back Jan 2006.
You can Tell this particularly with Ultimate 64, as of course each bit string is longer, using extra bandwidth, yet NOT Having enough Lanes & bandwidth for so Much Needed software/hardware Control.
More Bandwidth Now Needs ALL New Controllers, its 40 or 48 bit Today in enviorment Called ia64, NOT True 64 bit. Thats LAW Today. So to go as Fast AS Possible to 48 Lane Controllers & mere two 16X cards plus all other slots & plugs, would be BEST Bet for Well organized Vista Ultimate Main, However, ITS INSUFFIENT.
Better CPU is more instruction sets, yet it takes PINS, Making comparrison & Reaction Faster & Higher Speed Reaction & action I/O better. Faster Unit can Handle bettter(c+) naturally todays software, NOT with Other Side of MOON Cold, Better, Smoother & Stable Machine Will run & More Modules Each Software Package Can Handle When More is More thruout.How? Tell You..
For what appears all Writers in general sales point Pcie X, is full lanes & Fast, simplicity of Game Card Slot, EG ONE 32X slot beats ALL That Crump by ?Ultie Universe pundits & Good software needs ONE Slot, Not Million. ITS NOT THAT HARD, NOW THAT VISTA ULTIMATE IS OUT. Theres NO Choice, as xp is DEAD. Theres NO UP From Here WithOut Ultimate being Finalized & as certain poster in theINQ recently posted. BEST HOME BUILD IT YOURSELF Unit Today can I/O 500 Mb/s, while newness of SSD Brought forth to Public view two weeks ago SSD (by aggrevator search of the Register) SSD that STATED OUTPUT is 4.5 gb/s. So at BEST. Enthusist Child is Dabbing at 1/8 TOP Speed in Best of Worlds TOP Secret Labs, Yet Our Newbie Writers are obsessed by tweaking meaningless or Worse items, making confused mess out best their designed SLOw system can Muster.
ULTIEE’ Best would be from: mouths of ULIEE’ Ballmer year ago. This present ia64 is 32 bit with identifiers taken out. Something thomas stewart von drashek invented at George Mason Univesity in 1986 with CRAY XMP24 project, filling missing 8 bits with more true data bits, My latter invention: ia/ai 64 Formed From 2003 & by lastly taking out streaming idenitfiers year latter, to give effective 48 bitstring lenght every 40(bigger=Smoother) bit Blast to comparrisoon chip(faster=More Stable)), my idea as well, somewhere once in commentos disscussion in refining ia64 space, Now again Space Needs Redefining.
Yet heres point with Ballmer/Drashek ITS STILL NOT ENOUGH FOR TOP NOTCH COMPUTING, ESPECIALLY APPROACHING NT8 IN upcoming decade. Entire Machinerly needs to take next step, not 56, true 64 bitlength O/S not 32 + part of next, two full 32 bit strings blasting down multi pathway.
Copyright, Trademark & pat Pending. thomas stewart von drashek
SignedHYSICIAN THOMAS STEWART VON DRASHEK M.D.
To Reach 56 You’d add identifiers again, which corrects errors in first tests. yet As comparrison chip can be Bridged to work any bit string length it is designed to, from small to large, as long as ite in entire loom correctly, upswing dislocation could be minimalized. Ultiee’ P.P. concept 2008.
Long, yet seldom do Hales words MAKE ANY SENSE, ESPECILLY Such Clear Sense.
Signed: MM MD
Charlie? Is that you, Charlie?